1. Technical Field
The invention concerns a bipolar semiconductor device, in particular a vertical heterobipolar transistor (HBT). The invention further concerns a process for the production of such a bipolar semiconductor device.
2. Discussion of Related Art
The efficiency of silicon-based bipolar transistors (also referred to in English as: bipolar junction transistor or BJT) has been considerably improved in the high-speed range by novel structural element constructions and material components as well as reduction in structural size.
Essential features of modern vertical high-sped bipolar transistors are described in K Washio, ‘SiGe HBT and BiCMOS Technologies’, IEDM, pages 113-116, 2003.
Known design configurations include highly conductive base and collector connection regions which lead the charge carrier flow from the inner transistor region towards the corresponding contact regions. In order at the same time to ensure a low capacitance in respect of the base connection region in relation to the other electrical connections of the transistor the semiconductor regions are separated from each other by insulator regions with a low dielectric constant, for example by silicon dioxide. So-called double polysilicon technology or single polysilicon technology with differential base epitaxy have become established as the production processes for that structural feature.
The state of the art attained in that respect however, for both variants, requires a compromise between very low feed lead resistances on the one hand and very low capacitances or good values in respect of the functional transistor yield on the other hand.
That relationship is illustrated for the double polysilicon technology in relation to FIG. 1. FIG. 1 shows a cross-sectional view of a bipolar transistor in accordance with the state of the art, which in its essential features corresponds to the transistor of FIG. 1(a) from the above-mentioned publication by Washio. A collector region 20 adjoins downwardly a substrate 10 and laterally recesses 11 in the silicon, which are filled with silicon dioxide (SiO2) and which are also referred to as field insulation regions. In that respect, various design configurations in accordance with the state of the art use either shallow field insulation regions in the form of shallow trenches (referred to in English as shallow trench isolation or STI), as shown in FIG. 1, or alternatively deeper trenches, referred to as deep trenches.
In a vertical direction the collector region 20 is composed of a highly doped collector region 21 disposed at the substrate side and a lowly doped collector region 23 disposed thereabove. Portions 22 of a collector connection region adjoin the collector region in a lateral direction under the STI regions 11.
A window 34 is produced over the collector region 20 in a layer stack comprising a first insulator layer 30, a polysilicon layer 31 and a second insulator layer 32. By selective etching of the first insulator layer 30 a portion of the polysilicon layer 31, which projects laterally beyond the first insulator region 30, is produced at the lateral edge of the window 34. The ends of the overhanging portions of the polysilicon layer 31 are provided with spacers 50 of insulator material.
During a selective epitaxy step for the production of a base layer 40 silicon fronts grow at the same time from the exposed portions of the polysilicon layer 31 and the collector region 20 towards each other in a vertical direction and close the gap between the polysilicon layer 31 serving as part of the base connection region, and the inner transistor region.
A T-shaped emitter region 60, with a vertical portion which corresponds to the vertical bar of the T-shape, adjoins the base layer 40 downwardly and adjoins the spacers 50 laterally. Deposited over the SiGe layer is a cap layer which can receive dopants which diffuse in the production process out of the emitter and which can receive at least a part of the base-emitter space charge zone. The emitter-side boundary of the cap layer is indicated by a separation line in the emitter. Portions of the emitter 60, which correspond to the horizontal bar of the T-shape, rest sideways on the second insulator layer 32.
A further typical feature of that known transistor structure is a selectively implanted collector (SIC) region 33 in which the level of collector doping is locally raised in order at the same time to minimise the collector-base transit time, the base-collector capacitance and the collector resistance, in a way which permits good high-speed properties on the part of the transistor.
If consideration is given to the collector arrangement shown in FIG. 1, more weakly doped silicon regions 23 exist in the collector region laterally of the SIC region 33. The silicon regions 23, because of their increased electrical resistance, do not make any noticeable contribution to transport of the collector current, but at least in a part of the overhanging portions of the polysilicon layer 31 cause parasitic contributions to the base-collector capacitance.
That parasitic capacitance component could be reduced without disadvantages in terms of other transistor properties, if it were to be successfully possible to replace the low-doped silicon region laterally adjoining the SIC region by SiO2.
It would be possible to envisage manufacturing that apparatus feature by way of a reduction in the width of the inner collector region, more specifically in such a way that the opening of the first insulator layer 30 also extends partially over the STI regions 11, by the lateral boundary of the first insulator layer 30 projecting beyond the collector region.
Using the typical production procedures for that transistor structure however that process would involve consequences in terms of base resistance, which would be intolerably harmful, because the selective growth behaviour during the epitaxial step would mean that the full width of the gap under the overhanging portion of the polysilicon layer 31 would no longer be filled with silicon. Furthermore there is also a substantially increased danger that crystal defects project into the active transistor region and the functional transistor yield is thus adversely affected.
FIG. 2 shows a cross-sectional view of a further vertical bipolar transistor in accordance with the state of the art. FIG. 2 diagrammatically shows a portion of the inner transistor region as well as the adjoining base and collector connection regions. The transistor in FIG. 2 has a single polysilicon structure with differentially deposited base. Essential features of the collector structure are the same as those of the double polysilicon variant shown in FIG. 1.
A collector 120 is enclosed downwardly by a substrate 110 and towards the sides by STI regions 111. The collector 120 has a highly doped portion 121 at the substrate side. Towards the surface the collector has a lowly doped portion 123. Unlike the double polysilicon structure of FIG. 1 in which deposit of the polysilicon layer 31 is effected independently of that of the base layer, the single polysilicon variant provides that polycrystalline semiconductor material 130 is deposited during the differential epitaxy step for base production on the field insulation regions, and that polycrystalline semiconductor material 130 can be used as part of the base connection region.
The processes described in patent application No DE 10358046.8 to the present applicants, which has not yet been published, can be used for production of the emitter structure 160 shown in FIG. 2.
For the reasons described hereinbefore an SIC region 133 is used just as in the double polysilicon variant. The known single polysilicon transistor structures also typically have more weakly doped silicon regions in lateral proximity with the SIC region 133, which cause unwanted capacitance contributions between the base connection and collector region.
It will be noted however that the above-described procedure for reducing that parasitic capacitance, in which more specifically the lateral extent of the collector region were reduced with the width of the emitter window being maintained, would not inevitably cause an increase in the base resistance in the case of single polysilicon technology. With a displacement of the STI regions 111 however at the same time the limit between a layer stack grown in monocrystalline mode on the collector region 20 and comprising a buffer layer 140, a base layer 141 and a cover layer 142 and the silicon deposited in polycrystalline mode on the STI region would be displaced in the direction of the emitter 160. Accordingly the front of the dopant which diffuses out of the polysilicon 130 would also be displaced in the direction of the SIC region 133. Admittedly that procedure reduced the area of the horizontally extending part of the space charge zone between the base layer 141 and the collector region and consequently the associated capacitance contribution. Optimised arrangements in accordance with the state of the art however will not reap any benefit from that procedure because on the one hand the total capacitance could increase due to the increase in other components of the base-collector capacitance or because on the other hand the risk in respect of crystal defects in the inner transistor region could unacceptably rise. The last-mentioned disadvantage arises in particular due to the direction of growth of the crystal imperfections at the transition from the monocrystalline to polycrystalline semiconductor material during the differential epitaxy and due to indirect adjustment of the emitter relative to the collector region.
To sum up the following first aspect is emphasised in relation to the foregoing criticism in relation to the state of the art: both in the single and also the double polysilicon technology, there is no obvious possible way, due to the structure involved, of further minimising the base-collector capacitance by a variation in collector width without other properties which are necessary for best high-speed characteristics being considerably adversely affected.
Furthermore the known transistor arrangements shown in FIGS. 1 and 2 exhibit a second aspect which is open to criticism: the parts of the base connection, which are on the insulator region, comprise polycrystalline material, whereby contact and feed lead resistances are perceptibly increased in comparison with values for monocrystalline material.